Method of forming a lower electrode of a capacitor
US7629262B2 · kind B2 · utility
9Cited by
8References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2005 |
| Grant date | Dec 8, 2009 |
| Priority date | — |
| Expiry date | Aug 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
In an embodiment, a method of forming a lower electrode of a capacitor in a semiconductor memory device includes etching a mold oxide layer to have at a cylindrical structure, resulting in an electrode with increased surface area. The cylindrical structure may have more than one radius. This increased surface area results in an increased capacitance. An excessive etch phenomenon, which occurs because a sacrificial oxide layer is etched at a higher rate than the mold oxide layer, is avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.