Semiconductor memory device and manufacturing method therefor

US7629651B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventor

• Hiroomi Nakajima · Yokohama, JP

Key dates

• Filing date: Jun 8, 2007
• Grant date: Dec 8, 2009
• Expiry date: Jan 17, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/62

Abstract

This disclosure concerns a semiconductor memory comprising Fin-type semiconductor layers (Fins) provided on the insulation layer provided on a substrate; first gate insulation films provided on first side surfaces of the Fins; second gate insulation films provided on second side surfaces of the Fins, the second side surfaces being opposite sides of the first side surfaces of the Fins; front gate electrodes provided on the first side surfaces via the first gate insulation films; and back gate electrodes provided between a second side surface of one of the Fins and a second side surface of the other Fin which is adjacent to the one of the Fins, the second side surface of the one of the Fins is opposed to the second side surface of the other Fin, wherein widths of the front gate electrodes or the back gate electrodes are smaller than the feature size (F).