Noise reduction for switched capacitor assemblies
US7629837B2 · kind B2 · utility
0Cited by
8References
15Claims
0Family size
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Inventor
Key dates
| Filing date | Mar 7, 2008 |
| Grant date | Dec 8, 2009 |
| Priority date | — |
| Expiry date | Mar 7, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/26
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises an assembly of switched capacitors operated under control of a system clock signal. It further comprises a signal driver for generating a binary output signal at an output pad. The system clock signal is suppressed for a certain time period after each transition of the output signal, thereby preventing voltage droop generated by the transition to introduce noise in the signals of the assembly of switched capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.