Nand-structured flash memory
US7630261B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2007 |
| Grant date | Dec 8, 2009 |
| Priority date | — |
| Expiry date | Dec 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND-structured flash memory including a selection transistor having a first conducting path, one end of the first conducting path being connected to a bit line or a source line, at least one dummy gate having a second conducting path and a control gate, one end of the second conducting path being connected to the other end of the first conducting path of the selection transistor, a nonvolatile memory linked unit for storing external data, which includes a plurality of electrically erasable/writable nonvolatile memory cells having third conducting paths and control gates, the third conducting paths being connected in series, one end of the series of the third conducting paths being connected to the other end of the second conducting path of the dummy gate, a dummy gate driving circuit controlling a potential of the control gate of the dummy gate, and a memory cell driving circuit selectively driving the control gates of the plurality of nonvolatile memory cells to write, read or erase bit data for storing the external data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.