Signal line selection and polarity change of natural bit ordering in high-speed serial bit stream multiplexing and demultiplexing integrated circuits
US7630410B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2003 |
| Grant date | Dec 8, 2009 |
| Priority date | — |
| Expiry date | Apr 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A bit stream multiplexer and a bit stream demultiplexer of the present invention couples a communication Application Specific Integrate Circuit (ASIC) to a high-speed bit stream media. The bit stream multiplexer includes a first transmit data multiplexing integrated circuit having an input that receives a first plurality of bit streams at a first bit rate from the communication ASIC and an output that produces a second plurality of bit streams at a second bit rate, the second plurality having fewer bit streams than said first plurality. It further includes a second transmit data multiplexing integrated circuit having an input that receives the second plurality of bit streams at the second bit rate and an output that produces a single bit stream at a line bit rate, the single bit stream having a predetermined bit order. The bit stream demultiplexer includes similar demultiplexing integrated circuits. These circuits include an interface that may be ordered, have signal line polarities altered, or bit asserted states altered depending upon the particular implementation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.