Non-linear junction based electronics detection
US7630853B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2007 |
| Grant date | Dec 8, 2009 |
| Priority date | — |
| Expiry date | Oct 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/1319
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Line anomalies on a line under test are detected by generating a test signal at a first power level and coupling the test signal to the line under test. A response level is received from the line under test at a second and third harmonic frequency of the first test signal. A second test signal is generated at an increased power level and coupled to the line under test and a response level from the line is received at a second and third harmonic frequency of the second test signal. The process is repeated by raising the power level of the test signal until a current level supplied to the line by a test signal exceeds an acceptable threshold level. The response levels are compared to stored data to locate any line anomalies present. The stored data represents harmonic response data obtained from the same line at a previous time. A graphical or mathematical representation of the response data is produced such that the response data can be easily compared to locate any anomalies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.