Hybrid high-k gate dielectric film
US7632745B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2007 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Aug 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method of forming a gate dielectric film including: providing a channel region in a transistor, the channel region including multiple segments having different sizes, some of which belong to a first surface portion while others belong to a second surface portion wherein the first surface portion and the second surface portion are adjacent; forming a hybrid high-k gate dielectric film over the channel region including: forming a first dielectric material over the first surface portion, the first dielectric material having a sub-monolayer thickness; forming a second dielectric material over the second surface portion, the second dielectric material having a sub-monolayer thickness, and forming a third dielectric film over the first dielectric film and the second dielectric film wherein the third dielectric film is high-k.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.