Semiconductor unit having two device terminals for every one input/output signal
US7633147B2 · kind B2 · utility
57Cited by
4References
10Claims
0Family size
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Key dates
| Filing date | Sep 26, 2003 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Sep 26, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor unit constituting a memory device has a memory chip, a package substrate having three wiring layers. Power-supply surfaces (VDD surface) and (GND surface) are wired on the package substrate while an intra-package DQ bus is wired on an intermediate layer between both of the power-supply surfaces. The memory device has two DQ pins every one intra-package DQ bus. The intra-package DQ bus is connected to a signal terminal pad of the memory chip through a via hole. In view of the two DW pins, a via hole for connecting the intra-package DQ bus with the signal terminal pad constitutes a branch wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.