System and method for testing worst case transients in a switching-mode power supply
US7633277B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 2007 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Jun 17, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth a system and a method for testing the worst-case transients in the output voltage produced by a switching-mode power supply (SMPS). The system includes an SMPS and a dynamic load generator (DLG). The SMPS converts the input voltage into the output voltage by using a top field-effect transistor (FET) and a bottom FET. The worst case transients occur when the load being provided to the SMPS is turned on or off at the same time the top FET is turned off. The DLG is configured to monitor the edge of the gate voltage of the top FET and to turn the load provided to the SMPS on or off when the edge of the gate voltage of the top FET is falling. Consequently, the disclosed system is able to test the worst-case transients in the output voltage produced by the SMPS in a manner that is more reliable than prior art approaches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.