High-voltage dual-polarity I/O p-well pump ESD protection circuit
US7633731B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 8, 2008 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Jun 7, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
Abstract
An ESD protection circuit includes a discharge transistor formed in a p-well and having a drain coupled to the I/O pad, and a source coupled to ground. A MOS capacitor has a gate coupled to the I/O pad. A first resistor is coupled between the source and drain of the MOS capacitor and ground. A pulldown transistor has a drain coupled to the source and drain of the MOS capacitor, a source coupled to ground, and a gate coupled to a power-supply voltage node. A p-well control transistor has a source coupled to ground, and a drain coupled to the p-well. A second resistor is coupled between the I/O pad and the drain of the p-well control transistor. A pump transistor has a gate coupled to the gate of the discharge transistor, a drain coupled to the I/O pad, and a source coupled to the p-well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.