I/O descriptor cache for bus mastering I/O controllers
US7634587B2 · kind B2 · utility
6Cited by
10References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2004 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Nov 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/387
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that includes an I/O descriptor cache that is accessed by a bus mastering I/O controller. The I/O descriptor cache stores descriptors that describe data to be transferred during corresponding I/O operations. The system also includes an I/O controller configured to control one or more I/O devices. This I/O controller is configured to access I/O descriptors stored in the I/O descriptor cache without having to access the main memory, thereby conserving I/O bandwidth and power.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.