Packet processor that generates packet-start offsets to immediately store incoming streamed packets using parallel, staggered round-robin arbitration to interleaved banks of memory
US7634622B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2006 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Jan 4, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9089
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A shared memory stores packets for a packet processor. The shared memory is arranged into banks that are word-interleaved. All banks may be accessed in parallel during each time-slot by different requesters. A staggered round-robin arbiter connects requesters to banks in a parallel fashion. Requestor inputs to the arbiter are staggered to allow access to different banks in a sequential order over successive time-slots. Multi-processor tribes have many processors that generate random requests to the shared memory. A slot scheduler arranges these random requests into a stream of sequential requests that are synchronized to the staggered round-robin arbiter. A packet interface requestor stores incoming packets from an external network into the shared memory. The packet's offset within pages of the shared memory is determined by the first available bank that the packet can be written to, eliminating delays in storing incoming packets and spreading storage of frequently-accessed fields.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.