Multi-threaded processing design in architecture with multiple co-processors
US7634776B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2005 |
| Grant date | Dec 15, 2009 |
| Priority date | — |
| Expiry date | Nov 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/80
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a multi-threaded processing operation that includes, e.g., multimedia encoding/decoding, uses an architecture having multiple processors and optional hardware accelerators. The method includes the steps of: identifying a desired chronological sequence of processing stages for processing input data including identifying interdependencies of said processing stages; allotting each said processing sage to a processor; staggering the processing to accommodate the interdependencies; selecting a processing operation based on said allotting to arrive at a subset of possible pipelines that offer low average processing time; and, choosing one design pipeline from said subset to result in overall timing reduction to complete said processing operation. The invention provides a multi-threaded processing pipeline that is applicable in a System-on-Chip (SoC) using a DSP and shared resources such as DMA controller and on-chip memory, for increasing the throughput. The invention also provides an article which is programmed to execute the method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.