Non-volatile memory device and method of manufacturing the same
US7635633B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2007 |
| Grant date | Dec 22, 2009 |
| Priority date | — |
| Expiry date | Feb 11, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
Abstract
In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.