Continuous multigate transistors
US7635881B2 · kind B2 · utility
2Cited by
1References
14Claims
0Family size
Inventor
Key dates
| Filing date | Feb 28, 2008 |
| Grant date | Dec 22, 2009 |
| Priority date | — |
| Expiry date | Feb 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An N doped area neighboring to a P doped area on a semiconductor material, function respectively as a first gate and a second gate for transistors. A dielectric layer is made under the gates. A source and a drain are made under and near two sides of the dielectric layer, electrically coupled to the gate to form continuous multigate transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.