Dual gate structure, fabrication method for the same, semiconductor device having the same
US7635897B2 · kind B2 · utility
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2References
17Claims
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Key dates
| Filing date | Feb 14, 2006 |
| Grant date | Dec 22, 2009 |
| Priority date | — |
| Expiry date | Feb 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
Abstract
In one embodiment, a semiconductor device includes at least two stacked gate structures formed on a substrate. The two stacked gate structures each include a semiconductor layer and a metal layer over the semiconductor layer. The two stacked gate structures on the substrate are characterized by differential intermediate layers, one of the two structures including an ohmic layer and the other of the two structures not including an ohmic layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.