Semiconductor device
US7635912B2 · kind B2 · utility
5Cited by
7References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 17, 2008 |
| Grant date | Dec 22, 2009 |
| Priority date | — |
| Expiry date | Apr 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A resin layer covering a semiconductor chip on a wiring board is composed of a first resin layer and a second resin layer, wherein the first resin layer and the second resin layer differ in their plan view pattern, satisfying a relation of a<b, where “a” is difference in length in the direction from the center of the board towards the edges between the first resin layer and the second resin layer, and “b” is difference in length in the direction from the center of the board towards the corners between the first resin layer and the second resin layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.