Limiting amplifiers
US7636003B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 20, 2007 |
| Grant date | Dec 22, 2009 |
| Priority date | — |
| Expiry date | Mar 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45638
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A limiting amplifier with an input stage with dc offset cancellation, identical gain stages, an output buffer and a feedback filter. The input stage receives a differential input signal and outputs a first intermediate differential signal. The gain stages are cascaded to amplify the first intermediate differential signal and generate a second intermediate differential signal, amplified by the output buffer to produce an output signal. The feedback filter provides a dc offset voltage of the output signal to the input stage for the dc offset cancellation. The input stage comprises a resistor network coupled between a pair of input nodes and a power line and comprising a common resistor, a pair of load resistors and a shunt resistor. The load resistors share a common terminal connected to the common resistor that is connected to the power line. The shunt resistor has two terminals respectively connected to the load resistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.