Method of manufacturing metal insulating layer in semiconductor device
US7638422B2 · kind B2 · utility
0Cited by
3References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2006 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Jan 7, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76837
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a metal insulating layer of a semiconductor device relieves stress due to differential thermal expansion between insulating sub-layers by rounding off sharp edges formed between the sub-layers. A first metal insulating sub-layer is formed over a metal interconnection layer pattern. The first metal insulating sub-layer has sharp profiles due to a step height difference in the metal interconnection layer pattern. The first metal insulating sub-layer is wet etched to round off the sharp profiles. A second metal insulating sub-layer is formed over the first metal insulating sub-layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.