Semiconductor device
US7638869B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2007 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Sep 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1433
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a stacked arrangement of a substrate and a first chip and a second chip is disclosed. In one embodiment, the first chip is arranged with a lower face on an upper face of the substrate; the second chip with a lower face on an upper face of the first chip, whereby a partial area of the upper face of the first chip that is adjacent to an edge of the first chip is uncovered by the second chip; a fifth wire contact pad is arranged on the uncovered area of the upper face of the first chip; a first bonding wire is arranged that is connected with a first wire contact pad of the substrate and the fifth wire contact pad of the first chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.