Clock signal generation circuit and semiconductor device
US7639058B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2008 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Apr 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The semiconductor device is provided with a clock signal generation circuit that includes a reference clock signal generation circuit which generates a first reference clock signal, a first counter circuit which counts the number of rising edges of the first reference clock signal by using the first reference clock signal and a synchronizing signal, a second counter circuit which counts the number of rising edges of the first reference clock signal by using an enumerated value of the first counter circuit, a first divider circuit which divides a frequency of the first reference clock signal by using the enumerated value of the first counter circuit and generates a second reference clock signal, and a second divider circuit which divides a frequency of the second reference clock signal and generates a clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.