CMOS integrated super-heterodyne television receiver with multiple signal paths
US7639311B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 24, 2006 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Mar 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/189
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Integrated super-heterodyne television receivers with multiple signal paths implemented using CMOS technology. An integrated circuit, includes: a plurality of CMOS (Complementary Metal-Oxide Semiconductor) low noise amplifiers; an adjustable frequency source; and one or more down-conversion mixers coupled with the adjustable frequency source and the plurality of CMOS low noise amplifiers to form a plurality of super-heterodyne receiving paths between an input to the plurality of CMOS low noise amplifiers and an output from one or more down-conversion mixers; where the integrated circuit is implemented on a single chip of semiconductive substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.