Method and apparatus for providing synchronization in a communication system
US7639769B2 · kind B2 · utility
1Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2005 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Dec 29, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A dual loop, clock synchronization circuit for a receiver in a communication system. The circuitry uses a first loop of a digital phase lock loop for coarse synchronization to time stamps within the received data and uses a second loop for fine synchronization of a second numerically controlled oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.