Method of transforming serial scrambler to parallel scrambler, parallel scrambler and double-edge-triggered register with XOR operation
US7639801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2005 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Jul 31, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2201/70707
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of transforming a serial scrambler to a parallel scrambler, a parallel scrambler and a double-edge-triggered register with XOR operation are provided. The method transforms a serial scrambler to a parallel scrambler according to a characteristic polynomial:The method first determines a transformation formula:according to the parameters of the characteristic polynomial. The parallel bits Bj=[bMj, bMj+1, . . . , bMj+M−2, bMj+M−1] are arranged in order. The transformation number R=2t (the initial number of t is 0) is set. The parallel bits are replaced by the transformation formula. When (k−R)N+i+R(N−q) is larger than Mj−1 in the transformation formula, 1 is added to t in the transformation formula R=2t and the transformation formula is re-counted. Finally, the XOR gates are connected to the registers according to a computed result from the transformation formula.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.