Asynchronous clock domain crossing jitter randomiser
US7640151B2 · kind B2 · utility
2Cited by
7References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2004 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Oct 31, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for simulation of an electronic circuit is provided, the circuit being represented by a network of a plurality of logic elements, the circuit comprising first and second asynchronous clock domains, whereby jitter elements are additionally inserted at predetermined portions of circuit boundaries between the first and second clock domains, the jitter elements being represented as logic elements, the values of which are randomly set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.