Dynamic field patchable microarchitecture
US7640418B2 · kind B2 · utility
7Cited by
23References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2004 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Jan 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor memory architecture including a read-only memory (ROM) with programmed microcode and a random access memory (RAM) capable of storing microcode and one or more data bits used for the selection of corresponding ROM or RAM microcode for execution. A multiplexer receives input signals from both the ROM microcode and RAM microcode, and a control signal which is one or more RAM data bits is used to select from the RAM or ROM microcode inputs for further execution by the microprocessor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.