On-chip receiver eye finder circuit for high-speed serial link
US7640463B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2006 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Aug 21, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3171
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
In a high-speed serial link, an eye finder diagnostic circuit has improved performance by being on-chip with the existing capture latch(es) of a receive equalizer. The eye finder circuit employs an additional capture latch with its input tied to the same input node as the existing capture latch(es) of a receive equalizer. The additional capture latch has a clock input and reference voltage input. The clock input is adjusted through a phase interpolator (or variable delay line) while the reference voltage input is adjusted by a voltage generator. A digital post processing circuit then compares the output of the additional capture latch with the output of the other existing capture latch(es), in order to determine the receive eye opening. The horizontal eye opening is measured by changing the phase of the additional capture latch through the phase interpolator, while the vertical eye opening is measured by changing the reference voltage of the voltage generator of the additional capture latch. The eye finder circuit, being on-chip and in-line with existing capture latch(es), employs a minimum of power, minimum of area, and minimizes the extra loading to the existing equalizer output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.