Serialization of hardware and software debug data
US7640472B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2007 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Oct 7, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3672
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) having a link layer that (1) simultaneously receives both hardware debug data from on-chip ASIC logic and software debug data from an on-chip programmable processor and (2) serializes the hardware and software debug data streams to generate one or more serialized debug data streams, e.g., containing both hardware and software debug data, for output to off-chip debug testing equipment to support debug testing of both the ASIC logic and the programmable processor. Cross triggering can be implemented on-chip to support simultaneous display of correlated hardware and software debug information on appropriate monitors. The present invention supports debug testing using external debug testing equipment that does not require a hardware logic analyzer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.