Design flow for shrinking circuits having non-shrinkable IP layout
US7640520B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2007 |
| Grant date | Dec 29, 2009 |
| Priority date | — |
| Expiry date | Dec 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for processing an integrated circuit is provided. The method includes providing a first integrated circuit having a first scale, wherein the first integrated circuit comprises a shrinkable circuit comprising a first intellectual property (IP) layout, and a non-shrinkable circuit comprising a second IP layout; and generating a second integrated circuit having a second scale smaller than the first scale. The step of generating the second integrated circuit includes shrinking the shrinkable integrated circuit to the second scale. The method further includes merging the second IP layout with the non-shrinkable circuit to generate a final integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.