Mixed signal integrated circuit with improved isolation
US7642188B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 1, 2004 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Dec 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for reducing an effective lateral resistance of a buried layer in an IC includes forming first and second circuit sections in a common substrate, the second circuit section being spaced laterally from the first circuit section. The method further includes forming an isolation buried layer in the substrate under at least a portion of the first circuit section and forming a conductive layer on a surface of the substrate, the conductive layer overlaying at least a portion of the first circuit section. A plurality of conductive plugs are formed in the substrate for operatively connecting the isolation buried layer to the conductive layer, whereby an effective lateral resistance of the isolation buried layer is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.