System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors

US7642602B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• Ting Chieh Su · Nantou, CN
• Min-Chie Jeng · Taipei, TW
• Chin Chang Liao · Shanghai, CN
• Jun Cheng Huang · Shanghai, CN

Key dates

• Filing date: Oct 18, 2006
• Grant date: Jan 5, 2010
• Expiry date: Oct 13, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/514

Abstract

A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. Each of the plurality of gate regions intersects a polysilicon region.