Integrated circuit with depletion mode JFET
US7642617B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2005 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Nov 15, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/87
Abstract
An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device includes a channel region in the semiconductor layer spaced from, and having a peak concentration positioned a predetermined distance below, the upper surface. An associated method of manufacturing includes introducing p-type dopant into the semiconductor surface to form a p-well in which the NMOS device is formed and a source and a drain of the JFET device. N-type dopant is introduced into the semiconductor surface to form an n-type region of the NMOS device below the p-well and a gate region of the JFET device. P-type dopant is introduced into the semiconductor layer to simultaneously form a higher concentration p-type region in the p-well of the NMOS device and a channel region extending between the source and drain of the JFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.