Wafer test system wherein period of high voltage stress test of one chip overlaps period of function test of other chip
US7642800B2 · kind B2 · utility
6Cited by
4References
11Claims
0Family size
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Key dates
| Filing date | Aug 31, 2007 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Dec 10, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2884
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.