Analog phase-locked loop
US7642822B2 · kind B2 · utility
10Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2008 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Apr 3, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Aspects of the present invention are related, in general, to Type-III phase-locked loops. In particular, aspects of the present invention relate to analog Type-III phase-locked loop arrangements comprising at least two signal paths, wherein each signal path may correspond to a bandwidth partition and may be selected by a selector according to a bandwidth parameter value. According to one aspect of the present invention, a first signal path may correspond to a fast loop (wide closed-loop bandwidth), and a second signal path may correspond to a slow loop (narrow closed-loop bandwidth).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.