Delay inversely proportional to temperature timer circuit
US7642833B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2004 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Dec 31, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/54
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A timer circuit is disclosed. The timer, having a delay configured to track inversely with temperature of the memory device, includes a reference signal configured to increase in voltage, as the temperature of the memory device increases. The reference signal may be generated from a current that is derived from a bandgap reference circuit. The timer circuit includes a pull-down path made up of a plurality of selectable pull down transistors which are coupled to the reference signal at the gate. Resistance of the pull-down path is reduced as the reference signal is increased and the reduced resistance of the pull-down path decreases the delay of timer. A plurality of selectable delay elements may be preconfigured to adjust the delay and are coupled to the output path of the current starved inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.