Systems and methods for PLL linearity measurement, PLL output duty cycle measurement and duty cycle correction
US7642863B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 7, 2007 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Feb 5, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's.) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.