System and method for multiple-phase clock generation
US7642865B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2006 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Apr 4, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multiple phase clock circuit includes a multiple stage voltage controlled oscillator (VCO) and multiple clock dividers. The VCO is operative at a frequency ‘N’ times higher than the required output frequency and generates ‘M’ equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of ‘M×N’ equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output, thus maintaining the sequence of the output of the Johnson counters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.