Sequentially-accessed 1R/1W double-pumped single port SRAM with shared decoder architecture
US7643330B1 · kind B1 · utility
21Cited by
12References
20Claims
0Family size
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Key dates
| Filing date | Aug 14, 2007 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Apr 17, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth a synchronous two-port static random access memory (SRAM) design with the area efficiency of a one-port SRAM. By restricting both access ports to an edge-triggered, synchronous clocking regime, the internal timing of the SRAM can be optimized to allow high-performance double-pumped access to the SRAM storage cells. By double-pumping the SRAM storage cells, one read access and one write access are possible per clock cycle, allowing the SRAM to present two external ports, each capable of performing one transaction per clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.