Semiconductor memory device
US7643347B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2008 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Dec 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The semiconductor memory device related to an embodiment of the present invention including a memory string in which a plurality of memory cells are connected, a bit line connected to an end of the memory string, a power supply circuit which generates a voltage or a current related to an operation state of each memory cell, a sense amplifier which supplies a control voltage or a control current which controls an operation state of each memory cell via the bit line according to the voltage or the current generated in the power circuit, and a transient response adjustment circuit which adjusts the transient response characteristics of the voltage or the current generated in the power supply circuit when the sense amplifier supplies to the bit line the control voltage or the control current which shifts the memory string from a first operation state to a second operation state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.