Erase voltage generator circuit for providing uniform erase execution time and nonvolatile memory device having the same
US7643351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2008 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | May 6, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erase voltage generation circuit providing a uniform erase execution time and a non-volatile semiconductor memory device having the same, in which the erase voltage generation circuit includes a high voltage generation unit, a voltage level detection unit, an execution time checking unit and a discharging unit. The high voltage generation unit generates an erase voltage. The voltage level detection unit detects the erase voltage and generates a level detection signal. The level detection signal is activated when the erase voltage reaches a target voltage. The execution time checking unit generates an execution end signal that is activated in response to the lapse of an erase execution time from the activation of the level detection signal. The discharging unit discharges the erase voltage as a discharge voltage. The high voltage generation unit is disabled in response to the activation of the execution end signal, and the discharging unit is enabled in response to the activation of the execution end signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.