PCI express switch with encryption and queues for performance enhancement
US7643495B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 18, 2005 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Feb 16, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/0428
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A switching interface comprising a switch having an input and a plurality of outputs, and a memory associated with the switch. The switch is adapted to receive a packet from the input, the packet to be forwarded to a destination device coupled to a one of the plurality of outputs. The switch is responsive to store the packet in the associated memory. The switch is further responsive to a signal from the destination device to forward the packet from the associated memory to the destination device through the one of the plurality of outputs. Optionally, the switching interface may further comprise a packet encryption engine coupled between the input and the associated memory. Typically, the output devices coupled to the plurality of outputs will each have its own separate encryption process; in these scenarios the encryption engine will have logic for determining the appropriate encryption for the output device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.