Method and apparatus for synchronizing clock timing between network elements
US7643595B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2005 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Dec 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0664
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Network elements may be synchronized over an asynchronous network by implementing a master clock as an all digital PLL that includes a Digitally Controlled Frequency Selector (DCFS), the output frequency of which may be directly controlled through the input of a control word. The PLL causes the control word input to the master DCFS to be adjusted to cause the output of the master DCFS to lock onto a reference frequency. Information associated with the control word is transmitted from the master clock to the slave clocks which are also implemented as DCFSs. By using the transmitted information to recreate the master control word, the slaves may be made to assume the same state as the master DCFS without requiring the slaves to be implemented as PLLs. The DCFS may be formed as a digitally controlled oscillator (DCO) or as a Direct Digital Synthesizer (DDS).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.