Techniques for performing gain and phase correction in a complex radio frequency receiver
US7643600B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2006 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Jun 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03C3/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver (300) includes a first mixing digital-to-analog converter (DAC) (336, 332), a second mixing DAC (338, 334), a direct digital frequency synthesizer (DDFS) (302), a phase correction circuit (340), a selectable load (306) and a magnitude correction circuit (350). The first mixing DAC (336, 332) includes a first input for receiving an input signal, a second input for receiving a digital first local oscillator (LO) signal and an output. The second mixing DAC (338, 334) includes a first input for receiving the input signal, a second input for receiving a digital second local oscillator (LO) signal and an output. The DDFS (302) is configured to provide the first and second LO signals, which are quadrature signals. The phase correction circuit (340) is configured to provide a phase correction signal to a control input of the DDFS (302). The first selectable load (306) includes an input coupled to the output of the first mixing DAC (336, 332) and a control input. The magnitude correction circuit (350) is configured to provide a first magnitude correction signal to the control input of the first selectable load (306).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.