Digital implementation of fractional exponentiation
US7644116B2 · kind B2 · utility
1Cited by
6References
13Claims
0Family size
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Key dates
| Filing date | May 31, 2006 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Aug 21, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/556
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are digital processing apparatuses and techniques for estimating the fractional exponentiation of the base number 2, i.e., 2f where f is a fractional value. In one representative embodiment, a calculation is made of a folded quantity, which is equal to 1−f if f is greater than a specified threshold and is equal to f otherwise; then, a function of the folded quantity is calculated; and finally, the function of the folded quantity is subtracted from the fraction f and 1 is added. In another embodiment, 2f is approximated by calculating 1+f′ in the binary numbering system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.