Method and system for storing and retrieving a translation of target program instruction from a host processor using fast look-up of indirect branch destination in a dynamic translation system
US7644210B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Sep 19, 2006 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Sep 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Entries in the cache have a host instruction address and tags that may include a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction. The cache may be a software cache apportioned by software from the main processor memory or a hardware cache separate from main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.