Non-volatile solid-state memory controller
US7644251B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2005 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Sep 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller includes a volatile random access memory and translation hardware. The volatile random access memory includes a table having at least one entry. The at least one entry includes a portion of a physical address of a memory location at a NAND flash non-volatile solid-state memory. The volatile random access memory is accessible to the translation hardware. The translation hardware is configured to sum binary data bits of a portion of a logical address and a pointer value to determine a random access memory address of the at least one entry and is configured to determine the portion of the physical address of the memory location at the NAND flash non-volatile solid-state memory based at least in part on the random access memory address of the at least one entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.