Techniques for providing greater error protection to error-prone bits in codewords generated from irregular codes
US7644336B2 · kind B2 · utility
12Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Feb 4, 2006 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Aug 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1197
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Greater error protection is provided to error-prone bits that are generated from irregular soft-decoded error correction codes. Error protection is increased to error-prone bits that of interest in a particular system (e.g., parity check bits). One or more extra bits are added to each codeword in the encoding process. The one or more extra bits correspond to lower weights. The one or more extra bits are discarded after each codeword is decoded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.