Programmable logic device with performance variation compensation
US7644385B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2005 |
| Grant date | Jan 5, 2010 |
| Priority date | — |
| Expiry date | Apr 4, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to produce configuration data containing alternative configuration memory settings each of which is optimized for programmable logic devices with different performance characteristics. During manufacturing, programmable logic devices are tested to identify their performance characteristics. A bin code is stored in non-volatile memory in each device to specify which performance characteristics are associated with that device. During programming, the bin code of a given device is used to decide which of the alternative configuration memory settings are to be discarded. The retained subset of the configuration data is loaded into configuration memory in the given device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.