Gate structures of a non-volatile memory device and methods of manufacturing the same
US7646056B2 · kind B2 · utility
24Cited by
8References
10Claims
0Family size
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Key dates
| Filing date | Mar 15, 2006 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | Jul 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
Abstract
In a gate structure of a non-volatile memory device is formed, a tunnel insulating layer and a charge trapping layer are formed on a substrate. A composite dielectric layer is formed on the charge trapping layer and has a laminate structure in which first material layers including aluminum oxide and second material layers including hafnium oxide or zirconium oxide are alternately stacked. A conductive layer is formed on the composite dielectric layer and then a gate structure is formed by patterning the conductive layer, the composite dielectric layer, the charge trapping layer, and the tunnel insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.