Compact CMOS ESD layout techniques with either fully segmented salicide ballasting (FSSB) in the source and/or drain regions
US7646063B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2006 |
| Grant date | Jan 12, 2010 |
| Priority date | — |
| Expiry date | Jun 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
Abstract
Transistor structures for relatively even current balancing within a device and methods for fabricating the same are disclosed. These devices can be used in relatively compact MOSFET Electrostatic Discharge (ESD) protection structures, such as in snapback devices. One embodiment utilizes a salisided exclusion layer for segmentation of the source and/or drain diffusion areas, while the others utilize poly for segmentation of the source and/or drain area. Also, diffusion is used generically herein and, for example, includes implants. These techniques provide relatively good ESD tolerance while consuming a relatively small amount of area, and provide significant area and parasitic capacitance reduction over the state of the art without sacrificing ESD performance. These techniques are also applicable to current balancing within relatively high current devices, such as drivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.